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NXP Semiconductors

PCA9532

16-bit I 2 C-bus LED dimmer

7. Characteristics of the I 2 C-bus

The I 2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 7 ).

SDA

SCL

data line

stable;

change

of data

Fig 7.

Bit transfer

data valid

allowed

mba607

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is de?ned as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is de?ned as the STOP

condition (P) (see Figure 8 ).

SDA

SCL

START condition

STOP condition

mba608

Fig 8.

De?nition of START and STOP conditions

7.2 System con?guration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 9 ).

PCA9532_4

Product data sheet

Rev. 04 — 17 March 2009

10 of 29

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